The performance of an integrated circuit depends in part on the electrical properties of materials defining the circuit. One important region for many integrated circuits is the “active device region,” which is located close to the surface, e.g., of a semiconductor wafer. With increasing complexity of integrated circuits, this active device region may be formed by depositing a high quality film, typically an epitaxial layer, of the same material as the substrate (e.g., Si) or a compatible material such as SiGe (silicon-germanium). The top layer could also be a strain layer (strain silicon) or a film formed on an insulator (e.g., silicon-on-insulator or “SOI”). Such films may even be separated from the substrate by an air gap (e.g., “silicon-on-nothing” or “SON”). The thickness of the active device region scales with dimensions of the devices forming the integrated circuits. Smaller devices, which are required by the increasing density of integrated circuits, generally require a thinner active device region and a thinner high quality film or layer in which these devices are formed. Many advanced integrated circuits employ films that are no more than about 400 nm thick, with some of them having a thickness of 100 nm or less; such films are sometimes referred to herein as “thin active films.”
Achieving respectable manufacturing yields when using thin active films requires reliable information regarding the electrical properties of the thin active film. Electrical properties of the near-surface region of semiconductor materials are conventionally measured using capacitance vs. voltage (C-V) measurements. As schematically illustrated in FIG. 1, a small AC voltage VAC is applied to the semiconductor device 20, which is typified in FIG. 1 as a metal-oxide-semiconductor capacitor or “MOS-C,” using a measurement circuit 10. The measured current Jm may be used in a known fashion to determine the capacitance of the surface space-charge region. Simultaneously applied DC voltage VDC may be varied to modify this space-charge region and determine various electrical characteristics, including doping concentration. However, the C-V techniques cannot accurately measure the near-surface resistivity profile to less than about 2 to 3 Debye lengths from the surface (more than 500 nm for 10 ohm-cm silicon). (Dieter K. Schroder, “Semiconductor Material and Device Characterization,” John Wiley & Sons, Inc., New York 1990, Chapter 2). Measurements of average doping in the near-surface region are possible by so-called “Maximum-Minimum MOS-C Capacitance.” This method compares a maximum capacitance and a minimum capacitance for the tested specimen, which are achieved by applying the appropriate high electrical DC bias. Unfortunately, if this approach is used for non-contact measurements using an air gap, for example, the requisite electrical field can be high enough to cause electrical breakdown of and surface damage to the tested specimen.
Some known alternatives to the C-V technique are based on the surface photovoltage (SPV) effect described in U.S. Pat. Nos. 4,544,887; 4,827,212; 4,891,584; 5,087,876; 5,091,691; and 5,661,408, for example. These approaches are also extensively discussed in a number of publications, e.g., E. Kamieniecki, 1999; R. S. Nakhmanson, 1975; R. S. Nakhmanson at al., 1975; R. L. Streever at al., 1977; A. Sher at al., 1980; Ch. Munakata at al., 1981; E. Kamieniecki, 1982; E. Kamieniecki at al., 1983; E. Kamieniecki, 1983; O. Engstrom at al., 1983; E. Thorngren at al., 1984; Ch. Munakata at al., 1984; Ch. Munakata at al., 1984; H. Shimizu, 1987; E. Kamieniecki, 1989; E. Kamieniecki at al., 1993; and D. Marinskiy at al., 2000 (each of which is identified in the preceding bibliography). Currently, SPV techniques for measuring near-surface doping concentration use the surface photovoltage induced by an intensity modulated (or “chopped”), low-intensity, short-wavelength light beam (shown schematically as L in FIG. 2). This light beam L illuminates the semiconductor surface through a transparent, electrically conductive electrode 30 that is separated from the surface of the specimen 20 by a fraction of a millimeter. A near-surface depleted region D of the measured semiconductor is under depletion conditions, i.e., is depleted of majority carriers (electrons in n-type semiconductors and holes in p-type semiconductors). In some applications, the surface may also be strongly inverted, i.e., with minority carriers present at the surface. The depletion or depletion and inversion is achieved by forming a surface charge 25 of polarity corresponding to the majority carriers, as illustrated schematically in FIG. 3 for a p-type semiconductor 20. This charge could be associated with the natural state of the surface or it could be deposited, e.g., by corona charging. The electrical field in the semiconductor due to the surface charge repels majority carriers, leaving the depletion region D adjacent the surface.
The photon energy of the light beam L impinging on the semiconductor (FIG. 2) typically exceeds the energy gap of the semiconductor 20, which generates excess electron-hole pairs in the near-surface region. The electrical field present in the near-surface region causes excess minority carriers 26 (electrons in p-type semiconductors) to accumulate at the surface. The low-intensity, intensity modulated illumination plays a role analogous to that of AC voltage in a C-V technique. By keeping light intensity low enough, the charge from the accumulated carriers 26 caused by the light is much smaller than the pre-existing surface charge 25. As a result, the width of the depletion region D is not materially affected. An alternating current surface photovoltage (AC-SPV) generated with such low-intensity light is proportional to the dark (equilibrium) width of the depletion layer D (which, in turn, is proportional to the reciprocal of the space charge capacitance). This signal can be used as an equivalent of electrically measured capacitance. (See, e.g., U.S. Pat. No. 4,544,887.) If a near-surface region is depleted but the surface is not inverted, surface traps will substantially reduce accuracy of doping concentration measurements. With knowledge of the maximum depletion layer width (inverted conditions) under thermal equilibrium, typically determined empirically, one may determine the average doping concentration in the depletion region, similarly to the “Maximum-Minimum MOS-C Capacitance” method.
As noted above, thin active films in state-of-the-art semiconductor devices may have a thickness of 100 nm or less. Unfortunately, the maximum width of the depletion layer D0 under thermal equilibrium conditions may substantially exceed the thickness of a region of interest. For example, the width of the depletion region D0 may exceed, by an order of magnitude or more, the thickness of an active device region formed, e.g., by ion implantation in a near-surface region of silicon, in a thin active film of silicon epitaxial layer, in SiGe, in strain silicon, or in silicon-on-insulator (SOI).
Hence, conventional metrology techniques cannot effectively evaluate thin active films, which are a central part of next-generation integrated circuits. In the absence of a reliable, flexible metrology system, manufacturers likely will encounter poor yields of functioning devices with thin active films, driving up costs.